This application is based upon and claims priority from prior French Patent Application No. 9911895, filed Sep. 23, 1999, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to vertical bipolar transistors, especially those intended to be integrated into high-frequency very-large-scale integrated technologies (VLSI), and in particular to the production of the extrinsic base and of the emitter window of these transistors.
2. Description of Related Art
In polysilicon-emitter bipolar technologies, the emitter region generally comprises an emitter block having a narrower lower part located in a window, called the xe2x80x9cemitter windowxe2x80x9d, provided above the intrinsic base of the transistor. The emitter block also has a wider upper part which extends beyond the emitter window and rests on an insulating layer (generally formed from two insulating sublayers) above the base region.
Implantation of the extrinsic base takes place on either side of the wider, upper part of the emitter.
Next, the emitter window and the upper part of the emitter block are defined, using two separate photolithography levels which require two photolithography masks.
A diffused dopant zone is located beneath the emitter window of the emitter. In order to avoid contact between the diffused dopant zone and the boundary of the implanted zone of the extrinsic base, it is necessary, when producing the emitter, to specify a minimum distance between the boundaries of the emitter window and the boundaries of the upper part of the emitter block. This distance takes into account many parameters, especially the extension of the implanted zones during thermal anneals, as well as tolerances in the fabrication process.
Moreover, since two photolithography masks, i.e. two photolithography levels, are used, it is also necessary when defining the distance to take into account the alignment tolerance between the two photolithography masks.
Furthermore, taking this alignment tolerance into account requires the distance between the boundaries of the emitter window and the boundaries of the upper part of the emitter block to be increased so as to avoid any risk of contact between the diffused dopant zone beneath the emitter and the extrinsic base region.
Accordingly, this leads to the area of the intrinsic collector located between the two implanted extrinsic base zones being intentionally increased, with the consequence that the base-collector capacitance is increased.
Continuing further, taking into account this alignment tolerance also leads to the distance between the emitter window and the extrinsic base zones being intentionally increased, with the consequence that the base access resistance is increased.
All this leads to several shortcoming. One shortcoming is the dispersion in the characteristics of the transistor. Another shortcoming is inhomogeneity in the characteristics of the transistors fabricated from the same wafer. Yet, another shortcoming leads to degradation of the high-frequency performance of these transistors, such as, for example, the value of the maximum oscillation frequency (power gain cutout frequency).
These short comings have a penalizing effect on all types of vertical bipolar transistors, and most particularly for those intended to be integrated into high-frequency very-large-scale integrated technologies (VLSI), and which in this regard have an epitaxially grown base with a silicon-germanium (SiGe) heterojunction.
Accordingly, a need exists to overcome the shortcomings of the prior art where the extrinsic base is self-aligned with respect to the polysilicon emitter block but is not self-aligned with respect to the emitter window since two photolithography masks have been used, with the result that there is an alignment tolerance.
One object of the invention is to propose a way of fabricating a vertical bipolar transistor whose extrinsic base is self-aligned with respect to the emitter window, something which is not the case in the prior art that has just been mentioned.
Briefly, in accordance with the invention a process for fabricating a bipolar transistor comprising a phase of producing a base region having an extrinsic base and an intrinsic base and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base.
According to a general characteristic of the invention, the production of the extrinsic base comprises the implantation of dopants, carried out after definition of the emitter window, on either side of and at a predetermined distance from the lateral boundaries of the emitter window, so as to be self-aligned with respect to this emitter window and before the emitter block is formed.
The self-alignment with respect to the emitter window of the implanted extrinsic base is obtained because the emitter window is defined using a single photolithography mask and because this extrinsic base implantation is carried out before the emitter block is formed. The invention is therefore distinguished from the prior art which provided self-alignment of the extrinsic base not with respect to the emitter window but with respect to the polysilicon emitter block, and in which prior art the implantation of the extrinsic base was furthermore carried out after the emitter block was formed.
The invention applies to any type of vertical bipolar transistor, whatever the type of base used, whether this is a conventional silicon base or else a base with a silicon-germanium heterojunction, and any the method of producing the base, whether by implantation or epitaxy, for example.
According to one method of implementing the invention, an oxide block is produced on an insulating layer formed above the intrinsic base (this insulating layer possibly being formed, for example, from two insulating sublayers made of two different dielectrics, for example silicon dioxide and silicon nitride). The oxide block has a narrower lower part extending into an orifice etched in the insulating layer, the dimensions of the etched orifice corresponding to those of the emitter window. The oxide block also has a wider upper part resting on the insulating layer, the lateral edges of the etched orifice in the insulating layer being self-aligned with the lateral edges of the upper part of the oxide block. The implantation of the extrinsic base is then carried out on either side of the upper part of the oxide block. Self-alignment with respect to the upper part of the oxide block, and consequently self-alignment with respect to the lateral edges of the etched orifice and therefore of the emitter window, is therefore self-aligned.
A process for fabricating a bipolar transistor comprising the steps of: producing a base region comprising an extrinsic base and an intrinsic base; producing an emitter region above the intrinsic base comprising an emitter block with a narrower lower part located in an emitter window, the emitter window produced with vertical lateral boundaries; and implanting dopants in the extrinsic base before the emitter block is formed and after the production of the emitter window, so that dopants are implanted on either side of and at a predetermined distance from the vertical lateral boundaries of the emitter window, so that the extrinsic base is self-aligned with respect to the emitter window.
The insulating layer preferably comprises a first sublayer formed from a first silicon oxide (for example SiO2) above which is a second sublayer formed from a second dielectric (for example Si3N4). The spacers and the oxide block are formed from the first silicon oxide (for example SiO2). The etching of the cavity in the sacrificial layer and the etching of the spacers are carried out so as to stop on the second insulating sublayer (Si3N4). The orifice, whose dimensions correspond to those of the emitter window, is then etched in the second insulating sublayer (Si3N4).
The sacrificial layer may be made of polysilicon, or else of silicon-germanium, thereby making it easier to remove the sacrificial layer.
The sacrificial layer is preferably removed by isotropic plasma etching, using a gas mixture consisting of hydrobromic acid (HBr) and oxygen, in a volume ratio of the order of 10, at a pressure greater than 15 mTorr. In this way, very good selectivity both with respect to the material of the oxide block and with respect to the silicon nitride is obtained.
According to one method of implementing the invention, production of the emitter comprises etching of the oxide block and of that part of the insulating layer which is located in the emitter window, formation of a polysilicon layer on the unetched parts of the insulating layer and on that part of the intrinsic base which is located in the emitter window, and etching of the polysilicon layer so as to form the emitter block.
The base may be a base with a silicon-germanium heterojunction and formation of the base region may comprise epitaxy of a stack of silicon-germanium layers.
Moreover, according to one method of implementing the invention, production of the emitter may comprise epitaxy, on the emitter window, of the upper surface of the base stack so as to obtain, at least above the window, an emitter region formed from monocrystalline silicon and directly in contact with the upper layer of the stack.